MYX4DDR264M16HW Datasheet, PDF (25/51 Pages) –

8.10
1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to
memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
WRITE OPERATION
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock
cycle (WL = RL - 1CK) (see "READ COMMAND" on page 23). The starting column and bank addresses are
provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst.
During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following
the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±^tDQSS. Subsequent DQS
positive rising edges are timed, relative to the associated clock edge, as ±^tDQSS. ^tDQSS is specified with a
relatively wide range (25% of one clock cycle). All of the WRITE diagrams show the nominal case, and where
the two extreme cases (^tDQSS [MIN] and ^tDQSS [MAX]) might not be intuitive, they have also been included.
Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and
any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous
flow of input data. The first data element from the new burst is applied after the last element of a completed
burst. The new WRITE command should be issued x cycles after the first WRITE command, where x
equals BL/2.
DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 6 (page 26).
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the
BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However,
a WRITE BL = 8 operation (with auto precharge disabled) might be interrupted and truncated only by another
WRITE burst as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture of
DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated with any command except
another WRITE command.
Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles
required to meet ^tWTR is either 2 or ^tWTR/^tCK, whichever is greater. Data for any WRITE burst may be followed
by a subsequent PRECHARGE command. ^tWR must be met. ^tWR starts at the end of the data burst, regardless
of the data mask condition.
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
25
Form #: CSI-D-685 Document 005