MT47H256M4 Datasheet, PDF (98/131 Pages) Micron Technology – DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
READ
Figure 53: Bank Read – with Auto Precharge
CK#
CK
CKE
Command1
T0
NOP1
T1
T2
T3
T4
T5
T6
T7 T7n T8 T8n
tCK
tCH tCL
ACT
NOP1
READ2,3
NOP1
NOP1
NOP1
NOP1
NOP1
ACT
Address
RA
Col n
RA
4
A10
RA
RA
Bank address
Bank x
Bank x
AL = 1
CL = 3
tRCD
tRAS
tRC
tRTP
tRP
DM
Bank x
Case 1: ^tAC (MIN) and ^tDQSCK (MIN)
DQS, DQS#
DQ6
5 ^tRPRE
tDQSCK _(MIN)
tRPST
5
tLZ _(MIN)
tLZ _(MIN)
D_nO
tAC _(MIN)
tHZ _(MIN)
Case 2: ^tAC (MAX) and ^tDQSCK (MAX)
DQS, DQS#
DQ6
4-bit
prefetch
5
tRPRE ^{tDQSCK (MAX)}
tRPST ₅
tLZ _(MAX)
Internal ^{tLZ (MAX)}
precharge
D_nO
tAC _(MAX)
tHZ _(MAX)
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. The DDR2 SDRAM internally delays auto precharge until both ^tRAS (MIN) and ^tRTP (MIN)
have been satisfied.
4. Enable auto precharge.
5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
6. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
98
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