MT47H256M4 Datasheet, PDF (31/131 Pages) Micron Technology – DDR2 SDRAM

AC Timing Operating Specifications
Table 11: AC Operating Specifications and Conditions
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
V_DDQ = +1.8V ±0.1V, V_DD = +1.8V ±0.1V
AC Characteristics
-187E
-25E
-25
-3E
-3
-37E
-5E
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Clock
CL = 7 ^tCK (avg) 1.875 8.0
–
–
–
–
–
–
–
–
–
–
–
– ns 6, 7, 8,
cycle time _{CL = 6} t_{CK (avg) 2.5}
8.0
2.5 8.0 2.5 8.0
–
–
–
–
–
–
–
–
9
CL = 5 ^tCK (avg) 3.0 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 –
–
–
–
CL = 4 ^tCK (avg) 3.75 8.0 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0
CL = 3 ^tCK (avg) 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0
CK high-level width ^tCH (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 ^tCK 10
CK low-level width ^tCL (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 ^tCK
Half clock period
t_HP
MIN = lesser of ^tCH and ^tCL
MAX = n/a
ps
11
Absolute ^tCK
t_{CK (abs)}
MIN = ^tCK (AVG) MIN + ^tJITper (MIN)
ps
MAX = ^tCK (AVG) MAX + ^tJITper (MAX)
Absolute CK
t_{CH (abs)}
MIN = ^tCK (AVG) MIN × ^tCH (AVG) MIN + ^tJITdty (MIN)
ps
high-level width
MAX = ^tCK (AVG) MAX × ^tCH (AVG) MAX + ^tJITdty (MAX)
Absolute CK
t_{CL (abs)}
MIN = ^tCK (AVG) MIN × ^tCL (AVG) MIN + ^tJITdty (MIN)
ps
low-level width
MAX = ^tCK (AVG) MAX × ^tCL (AVG) MAX + ^tJITdty (MAX)
Period jitter
t_{JITper –90 90 –100 100 –100 100 –125 125 –125 125 –125 125 –125 125 ps}
12
Half period
t_{JITdty –75 75 –100 100 –100 100 –125 125 –125 125 –125 125 –150 150 ps}
13
Cycle to cycle
t_JITcc
180
200
200
250
250
250
250
ps
14
Cumulative error, ^tERR_2per –132 132 –150 150 –150 150 –175 175 –175 175 –175 175 –175 175 ps
15
2 cycles
Cumulative error, ^tERR_3per –157 157 –175 175 –175 175 –225 225 –225 225 –225 225 –225 225 ps
15
3 cycles
Cumulative error, ^tERR_4per –175 175 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps
15
4 cycles
Cumulative error, ^tERR_5per –188 188 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15, 16
5 cycles
Cumulative error, ^tERR_6– –250 250 –300 300 –300 300 –350 350 –350 350 –350 350 –350 350 ps 15, 16
6–10 cycles
10per
Cumulative error, ^tERR_11– –425 425 –450 450 –450 450 –450 450 –450 450 –450 450 –450 450 ps
15
11–50 cycles
50per