MT47H256M4 Datasheet, PDF (32/131 Pages) Micron Technology – DDR2 SDRAM

Table 11: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
V_DDQ = +1.8V ±0.1V, V_DD = +1.8V ±0.1V
AC Characteristics
-187E
-25E
-25
-3E
-3
-37E
-5E
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
DQS output access ^tDQSCK –300 +300 –350 +350 –350 +350 –400 +400 –400 +400 –450 +450 –500 +500 ps
19
time from CK/CK#
DQS read preamble ^tRPRE
MIN = 0.9 × ^tCK
MAX = 1.1 × ^tCK
t_{CK 17, 18,}
19
DQS read
postamble
t_RPST
MIN = 0.4 × ^tCK
MAX = 0.6 × ^tCK
t_{CK 17, 18,}
19, 20
CK/CK# to DQS
t_LZ1
Low-Z
MIN = ^tAC (MIN)
MAX = ^tAC (MAX)
ps 19, 21,
22
DQS rising edge to ^tDQSS
CK rising edge
MIN = –0.25 × ^tCK
MAX = +0.25 × ^tCK
t_CK
18
DQS input-high
pulse width
t_DQSH
MIN = 0.35 × ^tCK
MAX = n/a
t_CK
18
DQS input-low
pulse width
t_DQSL
MIN = 0.35 × ^tCK
MAX = n/a
t_CK
18
DQS falling to CK
rising: setup time
t_DSS
MIN = 0.2 × ^tCK
MAX = n/a
t_CK
18
DQS falling from
CK rising:
hold time
t_DSH
MIN = 0.2 × ^tCK
MAX = n/a
t_CK
18
Write preamble
setup time
t_WPRES
MIN = 0
MAX = n/a
ps 23, 24
DQS write
preamble
t_WPRE
MIN = 0.35 × ^tCK
MAX = n/a
t_CK
18
DQS write
postamble
t_WPST
MIN = 0.4 × ^tCK
MAX = 0.6 × ^tCK
t_{CK 18, 25}
WRITE command
–
to first DQS
transition
MIN = WL - ^tDQSS
t_CK
MAX = WL + ^tDQSS