MT47H256M4 Datasheet, PDF (100/131 Pages) Micron Technology – DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
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Figure 55: x16 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window
T1
CK#
CK
tHP1
LLDDSQQS#3
DQ (last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)4
DQ (last data valid)4
DQ (first data no longer valid)4
DQ0–DQ7 and LDQS collectively6
T2
T2n
T3
T3n
T4
tHP1
tDQSQ2
tHP1
tHP1
tDQSQ2
tHP1
tDQSQ2
tHP1
tDQSQ2
tQH5
tQH5
tQHS
tQH5
tQHS
T2
T2n
T3
T2
T2n
T3
T2
T2n
T3
tQH5
tQHS
T3n
T3n
T3n
tQHS
UUDDQQSS3#
DQ (last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (first data no longer valid)7
DQ (last data valid)7
DQ (first data no longer valid)7
DQ8–DQ15 and UDQS collectively6
Data valid
window
tDQSQ2
Data valid
window
tDQSQ2
Data valid
window
tDQSQ2
Data valid
window
tDQSQ2
tQH5
T2
T2
tQH5
tQHS
T2n
tQH5
tQHS
T3
tQH5
tQHS
T3n
T2n
T3
T3n
tQHS
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Notes:
1. ^tHP is the lesser of ^tCL or ^tCH clock transitions collectively when a bank is active.
2. ^tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3. DQ transitioning after the DQS transitions define the ^tDQSQ window. LDQS defines the
lower byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
100
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