MT47H256M4 Datasheet, PDF (121/131 Pages) Micron Technology – DDR2 SDRAM

Figure 76: PRECHARGE Command-to-Power-Down Entry
T0
T1
CK#
CK
Command
Valid
PRE
1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
T2
T3
NOP
Address
Valid
A10
CKE
SiAnlgl lbevasbnaknsk
t_{CKE (MIN)}
1 x ^tCK
Power-down1
entry
Don’t Care
Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × ^tCK after the
PRECHARGE command. Precharge power-down entry occurs prior to ^tRP (MIN) being sat-
isfied.
Figure 77: LOAD MODE Command-to-Power-Down Entry
T0
T1
T2
T3
T4
CK#
CK
Command
Valid
LM
NOP
NOP
Address
CKE
Valid1
tCKE _(MIN)
tRP2
tMRD
Power-down3
entry
Don’t Care
Notes:
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and ^tRP met prior to issuing LM command.
3. The earliest precharge power-down entry is at T3, which is after ^tMRD is satisfied.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
121
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