MT47H32M16CC3B Datasheet, PDF (82/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 36 (page 81). These specifications are applicable when the DLL is en-
abled for normal operation. DLL enable is required during power-up initialization and
upon returning to normal operation after having disabled the DLL for the purpose of
debugging or evaluation. Enabling the DLL should always be followed by resetting the
DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-
fore a READ command can be issued to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization to occur may result in a vio-
lation of the ^tAC or ^tDQSCK parameters.
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-
FRESH command should be followed by a PRECHARGE ALL command.
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 36. The normal drive
strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-
mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-
tion (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18
drive strength. This option is intended for the support of lighter load and/or point-to-
point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the dif-
ferential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-
ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-
ing; however, it may be tied to ground via a 20Ω to 10kΩ resistor. This function is also
used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =
0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 36. This feature is only applica-
ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and
timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored
by the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 36. When ena-
bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. When
disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-
moving output buffer current. The output disable feature is intended to be used during
I_DD characterization of read current.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
82
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