MT47H32M16CC3B Datasheet, PDF (40/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-
er, the input timing (in ns) references to the ^tCK (AVG) when determining the required number of clocks. The fol-
lowing input parameters are determined by taking the specified percentage times the ^tCK (AVG) rather than ^tCK:
t_IPW, t_DIPW, t_DQSS, t_DQSH, t_DQSL, t_DSS, t_DSH, t_{WPST, and} t_WPRE.
19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by
the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The
following parameters are required to be derated by subtracting ^tERR_5per (MAX): ^tAC (MIN), ^tDQSCK (MIN), ^tLZ_DQS
(MIN), ^tLZ_DQ (MIN), ^tAON (MIN); while the following parameters are required to be derated by subtracting
t_{ERR5per (MIN):} t_{AC (MAX),} t_{DQSCK (MAX),} t_{HZ (MAX),} t_{LZDQS (MAX),} t_{LZDQ (MAX),} t_{AON (MAX). The parameter}
t_{RPRE (MIN) is derated by subtracting} t_{JITper (MAX), while} t_{RPRE (MAX), is derated by subtracting} t_{JITper (MIN).}
The parameter ^tRPST (MIN) is derated by subtracting ^tJITdty (MAX), while ^tRPST (MAX), is derated by subtracting
t_{JITdty (MIN). Output timings that require} t_{ERR5per derating can be observed to have offsets relative to the clock;}
however, the total window will not degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. ^tHZ and ^tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (^tHZ) or begins driv-
ing (^tLZ).
22. ^tLZ (MIN) will prevail over a ^tDQSCK (MIN) + ^tRPRE (MAX) condition.
23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-
ded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-
ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on ^tDQSS.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either
be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above V_IH[DC]min), then it must not transition LOW (below V_IH[DC])
prior to ^tDQSH (MIN).
26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and
UDQS with DQ[15:8].
27. The data valid window is derived by achieving other specifications: ^tHP (^tCK/2), ^tDQSQ, and ^tQH (^tQH = ^tHP - ^tQHS).
The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can
be derived.
28. ^tQH = ^tHP - ^tQHS; the worst case ^tQH would be the lesser of ^tCL (ABS) MAX or ^tCH (ABS) MAX times ^tCK (ABS) MIN
- ^tQHS. Minimizing the amount of ^tCH (AVG) offset and value of ^tJITdty will provide a larger ^tQH, which in turn
will provide a larger valid data out window.
29. This maximum value is derived from the referenced test load. ^tHZ (MAX) will prevail over ^tDQSCK (MAX) + ^tRPST
(MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns
for each signal). There are two sets of values listed: ^tDS_a, ^tDH_a and ^tDS_b, ^tDH_b. The ^tDS_a, ^tDH_a values (for reference
only) are equivalent to the baseline values of ^tDS_b, ^tDH_b at V_REF when the slew rate is 2 V/ns, differentially. The
baseline values, ^tDS_b, ^tDH_b, are the JEDEC-defined values, referenced from the logic trip points. ^tDS_b is referenced
from V_IH(AC) for a rising signal and V_IL(AC) for a falling signal, while ^tDH_b is referenced from V_IL(DC) for a rising sig-
nal and V_IH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values
must be derated by adding the values from Table 31 (page 62) and Table 32 (page 63). If the DQS differential
strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using