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| MT47H32M16CC3B Datasheet, PDF (30/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM | |||
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512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications â IDD Parameters
5. Definitions for IDD conditions:
LOW
HIGH
Stable
VIN ⤠VIL(AC)max
VIN ⥠VIH(AC)min
Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT-option or on AT-op-
tion devices when operated outside of the range 0°C ⤠TC ⤠85°C:
When IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derat-
TC ⤠0°C ed by 2%; and IDD6 and IDD7 must be derated by 7%
When IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be de-
TC ⥠85°C rated by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
30
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2004 Micron Technology, Inc. All rights reserved.
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