MT47H64M16HR-25ELH Datasheet, PDF (79/132 Pages) Micron Technology – 1Gb: x4, x8, x16 DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 76). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may re-
sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to ^tRCD (MIN) by delaying the inter-
nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
detail in Posted CAS Additive Latency (AL) (page 82).
Examples of CL = 3 and CL = 4 are shown in Figure 35; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
Figure 35: CL
T0
T1
T2
T3
T4
T5
T6
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ
DO
DO
DO
DO
n
n+1
n+2
n+3
CL = 3 (AL = 0)
CK#
CK
Command
DQS, DQS#
DQ
T0
READ
T1
T2
T3
NOP
NOP
NOP
CL = 4 (AL = 0)
T4
T5
T6
NOP
NOP
NOP
DO
DO
DO
DO
n
n+1
n+2
n+3
Notes: 1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
Transitioning data
Don’t care
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. X 10/11 EN
79
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