MT47H64M16HR-25ELH Datasheet, PDF (100/132 Pages) Micron Technology – 1Gb: x4, x8, x16 DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
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Figure 53: x4, x8 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window
CK#
CK
T1
tHP1
DQS#
DQS3
T2
T2n
T3
T3n
T4
tHP1
tHP1
tHP1
tDQSQ2
tDQSQ2
tHP1
tDQSQ2
tHP1
tDQSQ2
DQ (last data valid)
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)
DQ (last data valid)
DQ (first data no longer valid)
tQH5
T2
T2
tQH5
tQHS
tQH5
tQHS
T2n
T3
T2n
T3
tQH5
tQHS
tQHS
T3n
T3n
All DQs and DQS collectively6
T2
T2n
T3
T3n
Earliest signal transition
Latest signal transition
Data
valid
window
Data
valid
window
Data
valid
window
Data
valid
window
Notes:
1. ^tHP is the lesser of ^tCL or ^tCH clock transitions collectively when a bank is active.
2. ^tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3. DQ transitioning after the DQS transition defines the ^tDQSQ window. DQS transitions at
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.
5. ^tQH is derived from ^tHP: ^tQH = ^tHP - ^tQHS.
6. The data valid window is derived for each DQS transition and is defined as ^tQH - ^tDQSQ.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. X 10/11 EN
100
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