MT47H64M16HR-25ELH Datasheet, PDF (117/132 Pages) Micron Technology – 1Gb: x4, x8, x16 DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 68: Power-Down
CK#
CK
Command
CKE
T1
T2
T3
T4
tCK
tCH
tCL
Valid1
NOP
tCKE _(MIN)2
tIH
Address
Valid
DQS, DQS#
T5
NOP
tIS
T6
T7
NOP
Valid
tCKE _(MIN)2 ^tIH
tXP3, tXARD4
tXARDS5
Valid
T8
Valid
Valid
DQ
DM
Enter
power-down
mode6
Exit
power-down
mode
Don’t Care
Notes:
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVATE
(or if at least one row is already active), then the power-down mode shown is active
power-down.
2. ^tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of ^tIS + 2 × ^tCK + ^tIH. CKE must not transition
during its ^tIS and ^tIH window.
3. ^tXP timing is used for exit precharge power-down and active power-down to any non-
READ command.
4. ^tXARD timing is used for exit active power-down to READ command if fast exit is selec-
ted via MR (bit 12 = 0).
5. ^tXARDS timing is used for exit active power-down to READ command if slow exit is se-
lected via MR (bit 12 = 1).
6. No column accesses are allowed to be in progress at the time power-down is entered. If
the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exit-
ing power-down mode for proper READ operation.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. X 10/11 EN
117
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