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| MT47H64M16HR-25ELH Datasheet, PDF (65/132 Pages) Micron Technology – 1Gb: x4, x8, x16 DDR2 SDRAM | |||
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1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 26: Nominal Slew Rate for tDS
DQS1
DQS#1
VDDQ
tDS
tDH
VIH(AC)min
VREF to AC
region
tDS
tDH
VIH(DC)min
VREF(DC)
Nominal
slew rate
Nominal
slew rate
VIL(DC)max
VIL(AC)max
VREF to AC
region
VSS
ǻTF
Setup slew rate
falling signal
=
VREF(DC) - VIL(AC)max
ǻTF
ǻTR
Setup slew rate
rising signal
=
VIH(AC)min - VREF(DC)
ǻTR
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 27: Tangent Line for tDS
DQS1
DQS#1
VDDQ
tDS
tDH
tDS
tDH
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
line
Tangent line
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangent line
Nominal line
ǻTF
VREF to AC
region
ǻTR
VSS
Setup slew rate
falling signal
=
Tangent line (VREF[DC] - VIL[AC]max)
ǻTF
Setup slew rate
rising signal
=
Tangent line (VIH[AC]min - VREF[DC])
ǻTR
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
PDF: 09005aef821ae8bf
1GbDDR2.pdf â Rev. X 10/11 EN
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2007 Micron Technology, Inc. All rights reserved.
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