MT46V32M8P-5BK Datasheet, PDF (77/91 Pages) Micron Technology – Double Data Rate (DDR) SDRAM

256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 33: WRITE-to-READ – Uninterrupting
CK#
CK
Command
T0
WRITE
T1 T1n
NOP
Address
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
DQ
DI
b
DM
t_{DQSS (MIN)}
DQS
t_DQSS
DQ
DI
b
DM
T2 T2n
NOP
T3
NOP
t_WTR
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
T4
READ
Bank a,
Col n
T5
NOP
CL = 2
CL = 2
CL = 2
T6 T6n
NOP
DO
n
DO
n
DO
n
Transitioning Data
Don’t Care
Notes:
1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. ^tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case ^tWTR is not required, and the READ
command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
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