MT46V32M8P-5BK Datasheet, PDF (73/91 Pages) Micron Technology – Double Data Rate (DDR) SDRAM

256Mb: x4, x8, x16 DDR SDRAM
Operations
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 30 on page 75 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 31 on page 76. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 32 on page 76.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, ^tWTR should be met, as shown in Figure 33
on page 77.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 34 on page 78.
Note that only the data-in pairs that are registered prior to the ^tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 35 on page 79.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, ^tWR should be met, as shown in
Figure 36 on page 80.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 37 on page 81 and Figure 38 on page 82. Only the data-in pairs regis-
tered prior to the ^tWR period are written to the internal array; any subsequent data-in
should be masked with DM, as shown in Figures 37 and 38. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until ^tRP is met.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
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