MT46V32M8P-5BK Datasheet, PDF (35/91 Pages) Micron Technology – Double Data Rate (DDR) SDRAM

Notes
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
1. All voltages referenced to V_SS.
2. Tests for AC timing, I_DD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and the
device operation are guaranteed for the full voltage range specified.
3. Outputs (except for I_DD measurements) measured with equivalent load:
Output
(V_OUT)
V_TT
50
Reference
point
30pF
4. AC timing and I_DD tests may use a V_IL-to-V_IH swing of up to 1.5V in the test environ-
ment, but input timing is still referenced to V_REF(or to the crossing point for CK/CK#),
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1 V/ns in the range between V_IL(AC) and V_IH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that
is, the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. All speed grades are not offered on all densities. Refer to page 1 for availability.
7. V_REF is expected to equal V_DDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on V_REF may not
exceed ±2% of the DC value. Thus, from V_DDQ/2, V_REF is allowed ±25mV for DC error
and an additional ±25mV for AC noise. This measurement is to be taken at the nearest
V_REF bypass capacitor.
8. V_TT is not applied directly to the device. V_TT is a system supply for signal termination
resistors, it is expected to be set equal to V_REF, and it must track variations in the DC
level of V_REF.
9. V_ID is the magnitude of the difference between the input level on CK and the input
level on CK#.
10. The value of V_IX and V_MP is expected to equal V_DDQ/2 of the transmitting device and
must track variations in the DC level of the same.
11. I_DD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle times at CL = 3 for -5B; CL = 2.5, -6/-6T/-75; and CL = 2,
-75E/-75Z speeds with the outputs open.
12. Enables on-chip refresh and address counters.
13. I_DD specifications are tested after the device is properly initialized and is averaged at
the defined cycle rate.
14. This parameter is sampled. V_DD = 2.5V ±0.2V, V_DDQ = 2.5V ±0.2V, V_REF = V_SS,
f = 100 MHz, T_A = 25°C, V_OUT(DC) = V_DDQ/2, V_OUT (peak-to-peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is
less than 0.5 V/ns, timing must be derated: ^tIS has an additional 50ps per each
100 mV/ns reduction in slew rate from the 500 mV/ns. ^tIH has 0ps added, that is, it
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B,
-6, and -6T, slew rates must be greater than or equal to 0.5 V/ns.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.