MT44K32M18 Datasheet, PDF (72/111 Pages) Micron Technology – 576Mb: x18, x36 RLDRAM 3

Mode Register 2 (MR2)
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576Mb: x18, x36 RLDRAM 3
Mode Register 2 (MR2)
Figure 35: MR2 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17 ... A4 A3 A2 A1 A0 Address Bus
21 20 19 18 17-5 4 3 2 1 0
0¹ 0¹ MRS Reserved WRITE En RTR
Mode Register (Mx)
M19 M18
00
01
10
11
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
M4 M3
00
01
10
11
WRITE Protocol
Single Bank
Dual Bank
Quad Bank
Reserved
M1 M0
READ Training Register
00
0-1-0-1 on all DQs
0 1 _{Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0}
10
Reserved
11
Reserved
M2 READ Training Register Enable
0 Normal RLDRAM Operation
1
READ Training Enabled
Note: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
READ Training Register (RTR)
The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a
predefined bit sequence on the output balls to aid in system timing calibration. MR2[2]
is the master bit that enables or disables access to the READ training register, and
MR2[1:0] determine which predefined pattern for system calibration is selected. If
MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When
MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pat-
tern that is defined by MR2[1:0].
Prior to enabling the RTR, all banks must be in the idle state (^tRC met). When the RTR is
enabled, all subsequent READ commands will output four bits of a predefined se-
quence from the RTR on all DQs. The READ latency during RTR is defined with the Data
Latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, suc-
cessive READ commands must be issued and satisfy ^tRTRS. Address balls A[19:0] are
considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0] must
access Bank 0 with each RTR READ command. ^tRC does not need to be met in between
RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are
allowed. When the last RTR READ burst has completed and ^tRTRE has been satisfied, an
MRS command can be issued to exit the RTR. Standard RLDRAM 3 operation may then
start after ^tMRSC has been met. The RESET function is supported when the RTR is ena-
bled.
If MR2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all DQs with each RTR READ
command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs and the
opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command.
Note: Enabling RTR may corrupt previously written data.
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
72
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