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MT44K32M18 Datasheet, PDF (17/111 Pages) Micron Technology – 576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
Table 4: IDD Operating Conditions and Maximum Limits
Notes 1–6 apply to the entire table
Description Condition
Standby
tCK = idle; All banks idle; No inputs
current
toggling
Clock active
standby cur-
rent
Operational
current: BL2
Operational
current: BL4
Operational
current: BL8
Burst refresh
current
CS# = 1; No commands; Bank ad-
dress incremented and half ad-
dress/data change once every four
clock cycles
BL = 2; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write se-
quence; Continuous data during
WRITE commands
BL = 4; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write se-
quence; Continuous data during
WRITE commands
BL = 8; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write se-
quence; Continuous data during
WRITE commands
Sixteen bank cyclic refresh using
Bank Address Control AREF proto-
col; Command bus remains in re-
fresh for all sixteen banks; DQs are
High-Z and at VDDQ/2; Addresses
are at VDDQ/2
Symbol
ISB1 (VDD) x18
ISB1 (VDD) x36
ISB1 (VEXT)
ISB2 (VDD) x18
ISB2 (VDD) x36
ISB2 (VEXT)
IDD1 (VDD) x18
IDD1 (VDD) x36
IDD1 (VEXT)
IDD2 (VDD) x18
IDD2 (VDD) x36
IDD2 (VEXT)
IDD3 (VDD) x18
IDD3 (VDD) x36
IDD3 (VEXT)
IREF1 (VDD) x18
IREF1 (VDD) x36
IREF1 (VEXT)
-093E
125
125
30
870
895
30
1175
1185
35
1205
1215
35
1300
NA
35
1550
1570
80
-093
125
125
30
870
895
30
1115
1125
35
1145
1155
35
1220
NA
35
1550
1570
80
-107E
125
125
30
815
835
30
1100
1110
35
1130
1140
35
1200
NA
35
1400
1420
75
-107
125
125
30
815
835
30
1045
1055
35
1075
1080
35
1130
NA
35
1400
1420
75
-125E
125
125
30
725
740
30
940
950
35
970
980
35
1030
NA
35
1230
1245
70
-125
125
125
30
725
740
30
915
925
35
Units Notes
mA
7
mA
mA
945
mA
950
35
1000 mA
NA
35
1230 mA
1245
70