MT44K32M18 Datasheet, PDF (101/111 Pages) Micron Technology – 576Mb: x18, x36 RLDRAM 3

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576Mb: x18, x36 RLDRAM 3
Mirror Function
Mirror Function
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Ta-
ble 1 (page 12) to see how the address and command balls are mirrored. The same balls
are mirrored on the x36 device.
Table 41: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
1
2
3
4
5
6
7
8
9
10
11
12
13
A
V_SS
V_DD
NF
V_DDQ
NF
V_REF
DQ7 V_DDQ DQ8
V_DD
V_SS RESET#
B
V_EXT
V_SS
NF
V_SSQ
NF
V_DDQ DM0 V_DDQ
DQ5
V_SSQ
DQ6
V_SS
V_EXT
C
V_DD
NF
V_DDQ
NF
V_SSQ
NF
DK0# DQ2
V_SSQ
DQ3 V_DDQ DQ4
V_DD
D
A13
V_SSQ
NF
V_DDQ
NF
V_SSQ
DK0
V_SSQ
QK0 V_DDQ DQ0
V_SSQ
A11
E
V_SS
CS#
V_SSQ
NF
V_DDQ
NF
MF QK0# V_DDQ DQ1 V_SSQ
A0
V_SS
F
A9
A5
V_DD
A4
A3 REF# ZQ WE# A1
A2
V_DD
NC¹
A7
G
V_SS
A18
A8
V_SS
BA0
V_SS
CK#
V_SS
BA1
V_SS
A6
A15
V_SS
H
A10
V_DD
A12
A17
V_DD
BA2
CK
BA3
V_DD
A16
A14
V_DD
A19
J
V_DDQ
NF
V_SSQ
NF
V_DDQ
NF
V_SS
QK1# V_DDQ DQ9
V_SSQ QVLD V_DDQ
K
NF
V_SSQ
NF
V_DDQ
NF
V_SSQ
DK1
V_SSQ
QK1 V_DDQ DQ10 V_SSQ DQ11
L
V_DD
NF
V_DDQ
NF
V_SSQ
NF
DK1# DQ12 V_SSQ DQ13 V_DDQ DQ14 V_DD
M
V_EXT
V_SS
NF
V_SSQ
NF
V_DDQ DM1 V_DDQ DQ15 V_SSQ DQ16
V_SS
V_EXT
N
V_SS
TCK
V_DD
TDO V_DDQ
NF
V_REF DQ17 V_DDQ
TDI
V_DD
TMS
V_SS
RESET Operation
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are disabled, ODT (R_TT) turns off
(High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK
cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH,
the DRAM must be reinitialized as though a normal power-up was executed. All refresh
counters on the DRAM are reset, and data stored in the DRAM is assumed unknown af-
ter RESET# has gone LOW.
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
101
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