MT44K32M18 Datasheet, PDF (19/111 Pages) Micron Technology – 576Mb: x18, x36 RLDRAM 3

Table 4: I_DD Operating Conditions and Maximum Limits (Continued)
Notes 1–6 apply to the entire table
Description Condition
Multibank BL = 4; Cyclic bank access using
write current: Quad Bank WRITE; Half of address
Quad bank bits change every two clock cycles;
write
Continuous data; Measurement is
taken during continuous WRITE;
Subject to ^tSAW specification
Operating
burst read
current
example
BL = 2; Cyclic bank access; Half of
address bits change every clock cy-
cle; Continuous data; Measure-
ment is taken during continuous
READ
Operating
burst read
current
example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during con-
tinuous READ
Operating
burst read
current
example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during con-
tinuous READ
Symbol
I_QBWR (V_DD) x18
I_QBWR (V_DD) x36
I_QBWR (V_EXT)
I_DD2R (V_DD) x18
I_DD2R (V_DD) x36
I_DD2R (V_EXT)
I_DD4R (V_DD) x18
I_DD4R (V_DD) x36
I_DD4R (V_EXT)
I_DD8R (V_DD) x18
I_DD8R (V_DD) x36
I_DD8R (V_EXT)
-093E
2965
3195
130
2250
2395
80
1740
1835
55
1450
NA
45
-093
2965
3195
130
2250
2395
80
1740
1835
55
1450
NA
45
-107E
2890
3000
115
2045
2180
75
1595
1685
55
1315
NA
40
-107
2890
3000
115
2045
2180
75
1595
1685
55
1315
NA
40
-125E
2525
2615
100
1785
1895
70
1400
1475
50
1175
NA
40
-125
2525
2615
100
Units Notes
mA
1785 mA
1895
70
1400 mA
1475
50
1175 mA
NA
40