PC28F512P30EFA Datasheet, PDF (71/92 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

512Mb, 1Gb, 2Gb: P30-65nm
Power and Reset Specifications
Power and Reset Specifications
V_CC should attain V_CCmin from V_SS simultaneously with or before applying V_CCQ, V_PP
during power up. V_CC should attain V_SS during power down. Device inputs should not
be driven before supply voltage = V_CCmin.
Power supply transitions should only occur when RST# is LOW. This protects the device
from accidental programming or erasure during power transitions.
Asserting RST# during a system reset is important with automated program/erase devi-
ces because systems typically expect to read from the device when coming out of reset.
If a CPU reset occurs without a device reset, proper CPU initialization may not occur.
This is because the device may be providing status information, instead of array data as
expected. Connect RST# to the same active LOW reset signal used for CPU initialization.
Because the device is disabled when RST# is asserted, it ignores its control inputs dur-
ing power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 32: Power and Reset
Parameter
RST# pulse width LOW
RST# LOW to device reset during erase
Symbol
t_PLPH
t_PLPH
Min
100
–
Max
–
25
Unit
ns
us
Notes
1, 2, 3, 4
1, 3, 4, 7
RST# LOW to device reset during program
V_CC Power valid to RST# de-assertion (HIGH)
–
25
t_VCCPH
300
–
1, 3, 4, 7
1, 4, 5, 6
Notes:
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if ^tPLPH is < ^tPLPH MIN, but this is not guaranteed.
3. Not applicable if RST# is tied to V_CC.
4. Sampled, but not 100% tested.
5. When RST# is tied to the V_CC supply, device will not be ready until ^tVCCPH after V_CC ≥
V_CCMIN.
6. When RST# is tied to the V_CCQ supply, device will not be ready until ^tVCCPH after V_CC ≥
V_CCMIN.
7. Reset completes within ^tPLPH if RST# is asserted while no ERASE or PROGRAM operation
is executing.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
71
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