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PC28F512P30EFA Datasheet, PDF (43/92 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm) | |||
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512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Table 15: WAIT Functionality Table (Continued)
Condition
All Writes
WAIT Delay
WAIT
High-Z
Notes
1, 2
Notes: 1. Active means that WAIT is asserted until data becomes valid, then deasserts.
2. When OE# = VIH during writes, WAIT = High-Z.
The WAIT delay (WD) bit controls the WAIT assertion delay behavior during synchro-
nous burst reads. WAIT can be asserted either during or one data cycle before valid data
is output on DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid
data (default). When WD is cleared, WAIT is de-asserted during valid data.
Burst Sequence
The burst sequence (BS) bit selects linear burst sequence (default). Only linear burst se-
quence is supported. The synchronous burst sequence for all burst lengths, as well as
the effect of the burst wrap (BW) setting are shown below.
Table 16: Burst Sequence Word Ordering
Start
Address
(DEC)
0
1
2
3
4
5
6
7
â®
14
15
â®
0
1
2
3
Burst
Wrap
(RCR3)
0
0
0
0
0
0
0
0
â®
0
0
â®
1
1
1
1
4-Word Burst
(BL[2:0] =
0b001)
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
â®
â®
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
Burst Addressing Sequence (DEC)
8-Word Burst
(BL[2:0] = 0b010)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
â®
â®
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
16-Word Burst
(BL[2:0] = 0b011)
0-1-2-3-4â¦14-15
1-2-3-4-5â¦15-0
2-3-4-5-6â¦15-0-1
3-4-5-6-7â¦15-0-1-2
4-5-6-7-8â¦15-0-1-2-3
5-6-7-8-9â¦15-0-1-2-3-4
6-7-8-9-10â¦15-0-1-2-3-4-5
7-8-9-10â¦15-0-1-2-3-4-5-6
â®
14-15-0-1-2â¦12-13
15-0-1-2-3â¦13-14
â®
0-1-2-3-4â¦14-15
1-2-3-4-5â¦15-16
2-3-4-5-6â¦16-17
3-4-5-6-7â¦17-18
Continuous Burst
(BL[2:0] = 0b111)
0-1-2-3-4-5-6-â¦
1-2-3-4-5-6-7-â¦
2-3-4-5-6-7-8-â¦
3-4-5-6-7-8-9-â¦
4-5-6-7-8-9-10â¦
5-6-7-8-9-10-11â¦
6-7-8-9-10-11-12-â¦
7-8-9-10-11-12-13â¦
â®
14-15-16-17-18-19-20-â¦
15-16-17-18-19-20-21-â¦
â®
0-1-2-3-4-5-6-â¦
1-2-3-4-5-6-7-â¦
2-3-4-5-6-7-8-â¦
3-4-5-6-7-8-9-â¦
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
43
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© 2013 Micron Technology, Inc. All rights reserved.
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