PC28F512P30EFA Datasheet, PDF (56/92 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

512Mb, 1Gb, 2Gb: P30-65nm
Common Flash Interface
Table 26: Burst Read Information (Continued)
Hex Offset
P = 10Ah
(P+1F)h
(P+20)h
(P+21)h
(P+22)
Length
1
1
1
1
Description
Synchronous mode read capability configuration
1:
Bits 3 - 7 = Reserved.
Bits 0 - 2 = n where 2ⁿ⁺¹ hex value represents the
maximum number of continuous synchronous
reads when the device is configured for its maxi-
mum word width.
A value of 07h indicates that the device is capa-
ble of continuous linear bursts that will output
data until the internal burst counter reaches the
end of the device’s burstable address space.
This fields’s 3-bit value can be written directly to
the Read Configuration Register bits 0 - 2 if the
device is configured for its maximum word width.
See offset 28h for word width to determine the
burst data output width.
Synchronous mode read capability configuration
2.
Synchronous mode read capability configuration
3.
Synchronous mode read capability configuration
4.
Address
129:
12A:
12B:
12C:
Hex
Code
- -01
- -02
- -03
- -07
ASCII Value
(DQ[7:0])
4
8
16
Continued
Table 27: Partition and Block Erase Region Information
Hex Offset
P = 10Ah
Bottom
Top
(P+23)h
(P+23)h
Description
Optional Flash features and commands
Number of device hardware-partition regions
within the device:
x = 0: a single hardware partition device (no
fields follow).
x specifies the number of device partition regions
containing one or more contiguous erase block
regions
Length
1
Address
Bottom
Top
12D:
12D:
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
56
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.