MT40A1G8WE-075E Datasheet, PDF (67/358 Pages) Micron Technology – Refresh time of 8192-cycle at TC temperature range

8Gb: x8, x16 Automotive DDR4 SDRAM
DLL-On/Off Switching Procedures
DLL-On/Off Switching Procedures
The DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for
subsequent operations until the A0 bit is set back to 1.
DLL Switch Sequence from DLL-On to DLL-Off
To switch from DLL-on to DLL-off requires the frequency to be changed during self re-
fresh, as outlined in the following procedure:
1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to dis-
able the DLL, the DRAM on-die termination resistors, R_TT(NOM), must be in High-Z
before MRS to MR1.)
2. Set MR1 bit A0 to 1 to disable the DLL.
3. Wait ^tMOD.
4. Enter self refresh mode; wait until ^tCKSRE/^tCKSRE_PAR is satisfied.
5. Change frequency, following the guidelines in the Input Clock Frequency Change
section.
6. Wait until a stable clock is available for at least ^tCKSRX at device inputs.
7. Starting with the SELF REFRESH EXIT command, CKE must continuously be reg-
istered HIGH until all ^tMOD timings from any MRS command are satisfied. In ad-
dition, if any ODT features were enabled in the mode registers when self refresh
mode was entered, the ODT signal must continuously be registered LOW until all
t_{MOD timings from any MRS command are satisfied. If RTT(NOM) was disabled in}
the mode registers when self refresh mode was entered, the ODT signal is "Don't
Care."
8. Wait ^tXS_FAST, ^tXS_ABORT, or ^tXS, and then set mode registers with appropriate
values (an update of CL, CWL, and WR may be necessary; a ZQCL command can
also be issued after ^tXS_FAST).
• ^tXS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and
WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in
MR3 may be accessed provided the device is not in per-DRAM addressability
mode. Access to other device mode registers must satisfy ^tXS timing.
• ^tXS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh
and does not increment the refresh counter. The controller can issue a valid
command after a delay of ^tXS_ABORT. Upon exiting from self refresh, the device
requires a minimum of one extra REFRESH command before it is put back into
self refresh mode. This requirement remains the same regardless of the MRS bit
setting for self refresh abort.
• ^tXS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8,
RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.
9. Wait ^tMOD to complete.
The device is ready for the next command.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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