MT40A1G8WE-075E Datasheet, PDF (327/358 Pages) Micron Technology – Refresh time of 8192-cycle at TC temperature range

8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 151: DDR4-2133 Speed Bins and Operating Conditions
DDR4-2133 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
ACTIVATE-to-ACTIVATE or REFRESH
command period
READ:
nonDBI READ: DBI WRITE
CL = 9 CL = 11
CWL = 9
CL = 10 CL = 12
CWL = 9
CL = 11 CL = 13
CWL = 9 , 11
CL = 12 CL = 14
CWL = 9, 11
CL = 13 CL = 15
CWL = 10, 12
CL = 14 CL = 16
CWL = 10, 12
CL = 14 CL = 17
CWL = 11, 14
CL = 15 CL = 18
CWL = 11, 14
CL = 16 CL = 19
CWL = 11, 14
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
Symbol
t_AA
t_{AA_DBI}
t_RCD
t_RP
t_RAS
t_RC7
Symbol
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
-093F
14-14-14
Min
Max
13.13
19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
13.13
–
13.13
33
–
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
Reserved
1.071 <1.25
0.937⁶ <1.071
0.937 <1.071
0.937 <1.071
9, 10, 12, 14–16
11, 12, 14, 16–19
9, 10, 11, 12, 14
-093E
15-15-15
Min
Max
14.06⁵ 19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
14.06⁵
–
14.06⁵
33
–
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
1.25
<1.5
1.25
<1.5
1.071 <1.25
1.071 <1.25
Reserved
0.937 <1.071
0.937 <1.071
9–16
11–16,18,19
9, 10, 11, 12, 14
-093
16-16-16
Min
Max
15.00
19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
15.00
–
Unit
ns
ns
ns
15.00
–
ns
33
9 × ^tREFI ns
t_{RAS +}
–
ns
t_RP
Min
Max
Reserved
1.5
1.9
Reserved
1.25
<1.5
Reserved
1.071 <1.25
Reserved
Reserved
0.937 <1.071
10, 12, 14, 16
12, 14, 16, 19
9, 10, 11, 12, 14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
nCK
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. ^tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation 13.92ns
with CL13 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
t_{CK (MIN) = 0.938ns and} t_{RP = 14.06ns, then} t_{RP would require 15nCKs (14.06ns/0.938ns),}
but if ^tCK (MIN) = 0.937ns and ^tRP = 14.06ns, then ^tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
7. When calculating ^tRC and ^tRP in clocks, values may not be used in a combination that
would violate ^tRAS.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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