MT40A1G8WE-075E Datasheet, PDF (65/358 Pages) Micron Technology – Refresh time of 8192-cycle at TC temperature range

8Gb: x8, x16 Automotive DDR4 SDRAM
NOP Command
18. Idle state is defined as all banks are closed (^tRP, ^tDAL, and so on, satisfied), no data
bursts are in progress, CKE is HIGH, and all timings from previous operations are satis-
fied (^tMRD, ^tMOD, ^tRFC, ^tZQinit, ^tZQoper, ^tZQCS, and so on), as well as all self refresh ex-
it and power-down exit parameters are satisfied (^tXS, ^tXP, ^tXSDLL, and so on).
19. Self refresh mode can be entered only from the all banks idle state.
20. For more details about all signals, see the Truth Table – Command table; must be a legal
command as defined in the table.
NOP Command
The NO OPERATION (NOP) command was originally used to instruct the selected
DDR4 SDRAM to perform a NOP (CS_n = LOW and ACT_n, RAS_n/A16, CAS_n/A15, and
WE_n/A14 = HIGH). This prevented unwanted commands from being registered during
idle or wait states. NOP command general support has been removed and the com-
mand should not be used unless specifically allowed, which is when exiting maximum
power-saving mode or when entering gear-down mode.
DESELECT Command
The deselect function (CS_n HIGH) prevents new commands from being executed;
therefore, with this command, the device is effectively deselected. Operations already in
progress are not affected.
DLL-Off Mode
DLL-off mode is entered by setting MR1 bit A0 to 0, which will disable the DLL for sub-
sequent operations until the A0 bit is set back to 1. The MR1 A0 bit for DLL control can
be switched either during initialization or during self refresh mode. Refer to the Input
Clock Frequency Change section for more details.
The maximum clock frequency for DLL-off mode is specified by the parameter
t_{CKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the re-}
fresh interval, ^tREFI.
Due to latency counter and timing restrictions, only one CL value and CWL value (in
MR0 and MR2 respectively) are supported. The DLL-off mode is only required to sup-
port setting both CL = 10 and CWL = 9.
DLL-off mode will affect the read data clock-to-data strobe relationship (^tDQSCK), but
not the data strobe-to-data relationship (^tDQSQ, ^tQH). Special attention is needed to
line up read data to the controller time domain.
Compared with DLL-on mode, where ^tDQSCK starts from the rising clock edge (AL +
CL) cycles after the READ command, the DLL-off mode ^tDQSCK starts (AL + CL - 1) cy-
cles after the READ command. Another difference is that ^tDQSCK may not be small
compared to ^tCK (it might even be larger than ^tCK), and the difference between ^tDQSCK
(MIN) and ^tDQSCK (MAX) is significantly larger than in DLL-on mode. The ^tDQSCK
(DLL-off) values are vendor-specific.
The timing relations on DLL-off mode READ operation are shown in the following dia-
gram, where CL = 10, AL = 0, and BL = 8.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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