MT40A1G8WE-075E Datasheet, PDF (131/358 Pages) Micron Technology – Refresh time of 8192-cycle at TC temperature range

8Gb: x8, x16 Automotive DDR4 SDRAM
sPPR Row Repair
The bank receiving sPPR change is expected to retain memory array data in all rows ex-
cept for the seed row and its associated row addresses. If the data in the memory array
in the bank under sPPR repair is not required to be retained, then the handling of the
seed row’s associated row addresses is not of interest and can be ignored. If the data in
the memory array is required to be retained in the bank under sPPR mode, then prior to
executing the sPPR mode, the seed row and its associated row addresses should be
backed up and subsequently restored after sPPR has been completed. sPPR associated
seed row addresses are specified in the Table below; BA0 is not required by Micron
DRAMs however it is JEDEC reserved.
Table 43: sPPR Associated Rows
sPPR Associated Row Address
BA0*
A17
A16
A15
A14
A13
A1
A0
All banks must be precharged and idle. DBI and CRC modes must be disabled, and all
sPPR timings must be followed as shown in the timing diagram that follows.
All other commands except those listed in the following sequences are illegal.
1. Issue MR4[5] 1 to enter sPPR mode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key commands (shown in the table below) to MR0
with each command separated by ^tMOD. Please note that JEDEC recently added
the four guard key entry used for hPPR to sPPR entry; early DRAMs may not re-
quire four guard key entry code. A prudent controller design should accommo-
date either option in case an earlier DRAM is used.
a. Any interruption of the key sequence by other commands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR commands, sPPR will not be enabled, and the programming cycle
will result in a NOP.
c. When the sPPR entry sequence is interrupted and followed by ACT and WR
commands, these commands will be conducted as normal DRAM com-
mands.
d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a sup-
plier perspective and the user should rely on vendor datasheet.
Table 44: PPR MR0 Guard Key Settings
MR0
First guard key
Second guard key
Third guard key
Fourth guard key
BG1:0 BA1:0 A17:12 A11
A10
A9
A8
A7
A6:0
0
0
xxxxxx
1
1
0
0
1
1111111
0
0
xxxxxx
0
1
1
1
1
1111111
0
0
xxxxxx
1
0
1
1
1
1111111
0
0
xxxxxx
0
0
1
1
1
1111111
3. After ^tMOD, issue an ACT command with failing BG and BA with the row address
to be repaired.
4. After ^tRCD, issue a WR command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is a "Don't Care."
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
131
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