MT49H8M36 Datasheet, PDF (6/49 Pages) Micron Technology – 288Mb CIO Reduced Latency

288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II
Functional Block Diagram
Functional Block Diagram
Figure 2: 8 Meg x 36
A0–A18¹, B0, B1, B2
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh
Counter
Row Decoder
Memory Array
Bank 0
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Output Data Valid Output Data Clock
Input Buffers Output Buffers Control Logic and Timing Generator
QVLD
QK[1:0], QK#[1:0]
DQ0–DQ35
Notes: 1. When the BL = 4 setting is used, A18 is a “Don’t Care.“
PDF: 09005aef80a41b46/Source: 09005aef809f284b
MT49H8M36_2.fm - Rev. H 8/05 EN
6
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