MT49H8M36 Datasheet, PDF (34/49 Pages) Micron Technology – 288Mb CIO Reduced Latency

288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II
Configuration Table
Configuration Table
In multiplexed address mode, the read and write latencies are increased by one clock
cycle. The RLDRAM cycle time remains the same, as described in Table 14.
Table 14: Configuration Table In Multiplexed Address Mode
Frequency
400 MHz
300 MHz
200 MHz
Symbol
t_RC
t_RL
t_WL
t_RC
t_RL
t_WL
t_RC
t_RL
t_WL
t_RC
t_RL
t_WL
Configuration
1¹
2
4
6
5
7
6
8
20.0
23.3
26.7
20.0
30.0
25.0
35.0
35.0
40.0
Notes: 1. BL = 8 is not available for configuration 1.
3
8
9
10
20.0
22.5
25.0
26.7
30.0
33.3
40.0
45.0
50.0
Unit
cycles
cycles
cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
REFRESH Command in Multiplexed Address Mode
Similar to other commands, the REFRESH command is executed on the next rising clock
edge when in the multiplexed address mode. However, since only bank address is
required for AREF, the next command can be applied on the following clock. The opera-
tion of the AREF command and any other command is represented in Figure 32.
Figure 32: Burst REFRESH Operation
0
1
2
3
4
5
6
7
8
9
10
11
CK#
CK
CMD
AC
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AC
ADDR
Ax
Ay
Ax
Ay
BADDR BAk
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAk
Note:
AREF: AUTO REFRESH
AC: Any command
Ax: First part Ax of address
Ay: Second part Ay of address
BAk: Bank k; k is chosen so that ^tRC is met.
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MT49H8M36_2.fm - Rev. H 8/05 EN
34
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