MT49H8M36 Datasheet, PDF (38/49 Pages) Micron Technology – 288Mb CIO Reduced Latency

288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II
TAP Instruction Set
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded when it is placed between the TDI and TDO balls, as shown in Figure 36. Upon
power-up, the instruction register is loaded with the IDCODE instruction. It is also
loaded with the IDCODE instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are
loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test
data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed
between the TDI and TDO balls. This allows data to be shifted through the RLDRAM
with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the
RLDRAM. Several balls are also included in the scan register to reserved balls. The
RLDRAM has a 113-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state.
The Boundary Scan Order tables (see Table 21 on page 43) show the order in which the
bits are connected. Each bit corresponds to one of the balls on the RLDRAM package.
The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state
when the IDCODE command is loaded in the instruction register. The IDCODE is hard-
wired into the RLDRAM and can be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other information described in the Iden-
tification Register Definitions table on page 42.
TAP Instruction Set
Overview
Many different instructions (2⁸) are possible with the 8-bit instruction register. All used
combinations are listed in Table 20, Instruction Codes, on page 42. These six instruc-
tions are described in detail below. The remaining instructions are reserved and should
not be used.
The TAP controller used in this RLDRAM is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the Shift-IR state when the
instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR
state.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
MT49H8M36_2.fm - Rev. H 8/05 EN
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.