MT49H8M36 Datasheet, PDF (19/49 Pages) Micron Technology – 288Mb CIO Reduced Latency

288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II
Write Basic Information
Write Basic Information
Write accesses are initiated with a WRITE command, as shown in Figure 9. Row and
bank addresses are provided together with the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). A WRITE latency (WL) one cycle longer than the pro-
grammed READ latency (RL + 1) is present, with the first valid data registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command. Figures 13 and 14
illustrate the timing requirements for a WRITE followed by a READ for bursts of two and
four, respectively.
Setup and hold times for incoming DQ relative to the DK edges are specified as ^tDS and
t_{DH. The input data is masked if the corresponding DM signal is HIGH. The setup and}
hold times for data mask are also ^tDS and ^tDH.
Figure 9: WRITE Command
CK#
CK
CS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
DON’T CARE
Note: A: Address; BA: Bank address.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
MT49H8M36_2.fm - Rev. H 8/05 EN
19
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