PC28F00BP30EFA Datasheet, PDF (52/86 Pages) Micron Technology – Numonyx® Axcell™ P30-65nm Flash Memory

P30-65nm
Table 25: AC Read Specifications - (Sheet 2 of 2)
Num
Symbol
Parameter
Min Max Unit Notes
Synchronous Specifications (Easy BGA)⁽⁵⁾
R301
t_AVCH/L
Address setup to CLK
9
-
ns
R302
t_VLCH/L
ADV# low setup to CLK
9
-
ns
R303
t_ELCH/L
CE# low setup to CLK
9
-
ns
1,6
R304
t_CHQV/t_CLQV CLK to output valid
-
17
ns
R305
t_CHQX
Output hold from CLK
3
-
ns
R306
t_CHAX
Address hold from CLK
10
-
ns
1,4,6
R307
t_CHTV
CLK to WAIT valid
-
17
ns
1,6
R311
t_CHVL
CLK valid to ADV# Setup
3
-
ns
1
R312
t_CHTX
WAIT hold from CLK
3
-
ns
1,6
Notes:
1.
See Figure 15, “AC Input/Output Reference Waveform” on page 49 for timing measurements and max
allowable input slew rate.
2.
OE# may be delayed by up to t_ELQV – t_GLQV after CE#’s falling edge without impact to t_ELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst read mode is t_CHAX or t_VHAX, whichever timing specification is satisfied first.
5.
Synchronous burst read mode is not supported with TTL level inputs.
6.
Applies only to subsequent synchronous reads.
Figure 18: Asynchronous Single-Word Read (ADV# Low)
Address [A]
ADV#[V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P]
R1
R2
R3
R4
R15
R7
R6
R5
R8
R9
R17
Datasheet
52
Sept 2012
Order Number: 208042-06