MT48LC4M32B2 Datasheet, PDF (44/52 Pages) Micron Technology – SYNCHRONOUS DRAM

128Mb: x32
SDRAM
READ – FULL-PAGE BURST¹
T0
CLK
tCKS tCKH
CKE
T1
tCL
tCH
tCMS _tCMH
COMMAND
ACTIVE
NOP
T2
tCK
READ
DQM 0-3
tCMS tCMH
A0-A9, A11
tAS tAH
ROW
tAS tAH
A10
ROW
BA0, BA1
tAS tAH
BANK
COLUMN m ²
BANK
T3
NOP
DQ
tRCD
tAC
tLZ
CAS Latency
T4
NOP
T5
NOP
T6
( ( ^{Tn + 1}
))
((
))
((
))
((
))
((
))
NOP _{( (}
))
((
))
((
))
NOP
Tn + 2
Tn + 3
BURST TERM
NOP
Tn + 4
NOP
tAC
tOH
Dout m
tAC
tOH
DOUT m+1
((
))
((
))
((
))
((
))
((
))
((
))
tAC _{( (}
tOH ^{) )}
((
))
DOUT m+2_{( (}
))
tAC
tOH
DOUT m-1
tAC
tOH
DOUT m
256 locations within same row
Full page completed
Full-page burst does not self-terminate.
Can use BURST TERMINATE command. ³
tOH
DOUT m+1
tHZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_{AC (1)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
-6
MIN MAX
5.5
7.5
17
1
1.5
2.5
2.5
6
10
20
-7
MIN MAX
5.5
8
17
1
2
2.75
2.75
7
10
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
SYMBOL*
t_CKH
t_CKS
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_{HZ (1)}
t_LZ
t_OH
t_RCD
-6
MIN MAX
1
1.5
1
1.5
5
7.5
17
1
2
18
-7
MIN MAX
1
2
1
2
5.5
8
17
1
2.5
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. For this example, the CAS latency = 2.
2. A8, A9, and A11 = “Don’t Care.”
3. Page left open; no ^tRP.
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.