MT48LC4M32B2 Datasheet, PDF (40/52 Pages) Micron Technology – SYNCHRONOUS DRAM

128Mb: x32
SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE¹
T0
T1
T2
T3
T4
T5
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
DQM /
DQML, DQMH
A0-A9, A11
tAS tAH
ROW
tCMS tCMH
COLUMN m2
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
ALL BANKS
DISABLE AUTO PRECHARGE ^{SINGLE BANK}
BANK
BANK
ROW
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
tRP
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_{AC (1)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
t_CKS
-6
MIN MAX
5.5
7.5
17
1
1.5
2.5
2.5
6
10
20
1
1.5
*CAS latency indicated in parentheses.
-7
MIN MAX
5.5
8
17
1
2
2.75
2.75
7
10
20
1
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_{HZ (1)}
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
tOH
DOUTm
tHZ
DON’T CARE
-6
MIN MAX
1
1.5
5.5
7.5
17
1
2
42 120K
60
18
18
-7
MIN MAX
1
2
5.5
8
17
1
2.5
42 120K
70
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9, and A11 = “Don’t Care.”
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
40
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©2002, Micron Technology, Inc.