MT48LC4M32B2 Datasheet, PDF (29/52 Pages) Micron Technology – SYNCHRONOUS DRAM

128Mb: x32
SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
HXXX
L HHH
Idle
XXXX
Row
L L HH
Activating,
LHLH
Active, or
LHL L
Precharging L L H L
Read
L L HH
(Auto
LHLH
Precharge
LHL L
Disabled)
L LHL
Write
L L HH
(Auto
LHLH
Precharge
LHL L
Disabled)
L LHL
Read
L L HH
(With Auto
LHLH
Precharge)
LHL L
L LHL
Write
L L HH
(With Auto
LHLH
Precharge)
LHL L
L LHL
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
NOTES
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
NOTE:
1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Truth Table 2) and after ^tXSR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n
and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a
state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and ^tRP has been met.
Row Active: A row in the bank has been activated, and ^tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and
ends when ^tRP has been met. Once ^tRP is met, the bank will be in the idle state.
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.