MT48LC4M32B2 Datasheet, PDF (1/52 Pages) Micron Technology – SYNCHRONOUS DRAM

SYNCHRONOUS
DRAM
128Mb: x32
SDRAM
MT48LC4M32B2 - 1 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/sdramds
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3.
OPTIONS
• Configuration
4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package - OCPL¹
86-pin TSOP (400 mil)
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
• Operating Temperature Range
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
MARKING
4M32B2
TG
-6
-7
None
IT²
NOTE: 1. Off-center parting line
2. Available on -7
Part Number Example:
MT48LC4M32B2TG-7
KEY TIMING PARAMETERS
SPEED
CLOCK ACCESS TIME
GRADE FREQUENCY CL = 3*
-6
166 MHz
5.5ns
-7
143 MHz
5.5ns
*CL = CAS (READ) latency
SETUP
TIME
1.5ns
2ns
HOLD
TIME
1ns
1ns
PIN ASSIGNMENT (TOP VIEW)
86-PIN TSOP
VDD
1
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
VSSQ
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
VSSQ
12
DQ7
13
NC
14
VDD
15
DQM0
16
WE#
17
CAS#
18
RAS#
19
CS#
20
A11
21
BA0
22
BA1
23
A10
24
A0
25
A1
26
A2
27
DQM2
28
VDD
29
NC
30
DQ16
31
VSSQ
32
DQ17
33
DQ18
34
VDDQ
35
DQ19
36
DQ20
37
VSSQ
38
DQ21
39
DQ22
40
VDDQ
41
DQ23
42
VDD
43
86
VSS
85
DQ15
84
VSSQ
83
DQ14
82
DQ13
81
VDDQ
80
DQ12
79
DQ11
78
VSSQ
77
DQ10
76
DQ9
75
VDDQ
74
DQ8
73
NC
72
VSS
71
DQM1
70
NC
69
NC
68
CLK
67
CKE
66
A9
65
A8
64
A7
63
A6
62
A5
61
A4
60
A3
59
DQM3
58
VSS
57
NC
56
DQ31
55
VDDQ
54
DQ30
53
DQ29
52
VSSQ
51
DQ28
50
DQ27
49
VDDQ
48
DQ26
47
DQ25
46
VSSQ
45
DQ24
44
VSS
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 Meg x 32
1 Meg x 32 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.