MT48LC4M32B2 Datasheet, PDF (43/52 Pages) Micron Technology – SYNCHRONOUS DRAM

128Mb: x32
SDRAM
ALTERNATING BANK READ ACCESSES¹
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS _tCMH
COMMAND
ACTIVE
NOP
READ
NOP
DQM 0-3
tCMS tCMH
A0-A9, A11
tAS tAH
ROW
COLUMN m ²
T4
T5
T6
T7
ACTIVE
NOP
READ
NOP
ROW
COLUMN b²
T8
ACTIVE
ROW
A10
BA0, BA1
DQ
tAS tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 0
BANK 4
tAC
tAC
tOH
tAC
tOH
BANK 4
tAC
tOH
tAC
tOH
BANK 0
tAC
tOH
tRCD _{- BANK 0}
tRAS _{- BANK 0}
tRC _{- BANK 0}
tRRD
tLZ
CAS Latency - BANK 0
DOUT m
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP _{- BANK 0}
DOUT b
tRCD _{- BANK 0}
tRCD _{- BANK 4}
CAS Latency - BANK 4
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_{AC (1)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
-6
MIN MAX
5.5
7.5
17
1
1.5
2.5
2.5
6
10
20
1
-7
MIN MAX
5.5
8
17
1
2
2.75
2.75
7
10
20
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
t_CKS
t_CMH
t_CMS
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
t_RRD
-6
MIN MAX
1.5
1
1.5
1
2
42 120,000
60
18
18
12
-7
MIN MAX UNITS
2
ns
1
ns
2
ns
1
ns
2.5
ns
42 120,000 ns
70
ns
20
ns
20
ns
14
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8, A9, and A11 = “Don’t Care.”
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
43
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©2002, Micron Technology, Inc.