MT48LC4M32B2 Datasheet, PDF (16/52 Pages) Micron Technology – SYNCHRONOUS DRAM

T0
CLK
Figure 8
Random READ Accesses
T1
T2
T3
T4
128Mb: x32
SDRAM
COMMAND
READ
READ
READ
READ
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
CAS Latency = 1
DOUT
a
DOUT
x
DOUT
m
T0
T1
CLK
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
CAS Latency = 2
DOUT
x
DOUT
m
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DOUT
x
DOUT
m
DON’T CARE
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
16
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©2002, Micron Technology, Inc.