MT9VDDT6472HG Datasheet, PDF (11/18 Pages) Micron Technology – DDR SDRAM SODIMM

128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 11:
I_DD Specifications and Conditions – 256MB (Die Revision F)
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition
Symbol
Operating one bank active-precharge current:
t_{RC =} t_{RC (MIN);} t_{CK =} t_{CK (MIN); DQ, DM, and DQS inputs}
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one bank active-read-precharge current:
BL = 4; ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); I_OUT = 0mA; Address
and control inputs changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle;
t_{CK =} t_{CK (MIN); CKE = HIGH; Address and other control}
inputs changing once per clock cycle; V_IN = V_REF for DQ, DM,
and DQS
Active power-down standby current: One device bank
active; Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank active; ^tRC = ^tRAS (MAX); ^tCK = ^tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle; ^tCK = ^tCK (MIN); I_OUT = 0mA
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle; ^tCK = ^tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
Auto refresh current
t_{REFC =} t_RFC
(MIN)
t_{REFC = 7.8125µs}
Self refresh current: CKE  0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t_{RC =} t_{RC (MIN);} t_{CK =} t_{CK (MIN); Address and control inputs}
change only during active READ or WRITE commands
I_DD0
I_DD1
I_DD2P
I_DD2F
I_DD3P
I_DD3N
I_DD4R
I_DD4W
I_DD5
I_DD5A
I_DD6
I_DD7
-40B
1215
1530
36
540
360
630
1800
1755
2340
54
36
4230
-335
1125
1530
36
450
270
540
1575
1575
2295
54
36
3690
-262
1125
1440
36
405
225
450
1350
1350
2115
54
36
3150
-265
1080
Units
mA
1305
mA
36
mA
405
mA
270
mA
450
mA
1350
mA
1350
mA
2205
mA
54
36
mA
3285
mA
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. F 3/12 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved