MRF24J40 Datasheet, PDF (9/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

2.0 EXTERNAL CONNECTIONS
2.1 Oscillator
The MRF24J40 is designed to operate at 20 MHz with
a crystal connected to the OSC1 and OSC2 pins. A
typical oscillator circuit is shown in Figure 2-1.
FIGURE 2-1:
CRYSTAL OSCILLATOR
OPERATION
OSC1
C1
XTAL
To Internal
Logic
RS⁽¹⁾
C2
OSC2
MRF24J40
Note 1: A series resistor (RS) may be required for AT
strip cut crystals.
MRF24J40
2.2 Oscillator Start-up
The MRF24J40 PHY has an internal PLL that must lock
before the device is capable of transmitting or receiving
packets. After a full Power-on Reset, the device
requires 2 ms to lock. During this delay, all registers
and buffer memory may still be read and written to
through the SPI bus. However, software should not
attempt to transmit any packets (set the TXRTS
(TXNMTRIG<0>)), or access any MAC or PHY
registers during this period.
2.3 CLKOUT Pin
The clock out pin is provided to the system designer for
use as the host controller clock or as a clock source for
other devices in the system. The CLKOUT has an inter-
nal prescaler which can divide the output by 1, 2, 4 or 8.
The CLKOUT function is enabled via the CLKCTRL
register (Register 2-1) and the prescaler is selected via
the RFCTRL7 register (Register 2-2).
REGISTER 2-1:
R/W-0
r
bit 7
CLKCTRL: DIVIDED SLEEP CLOCK (50 kHz) SELECTION REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CLKOEN
SCLKDIV<4:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-0
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
CLKOEN: 20 MHz Clock Output Enable bit
1 = Disable
0 = Enable
SCLKDIV4:SCLKDIV0: Divided SLPCLK Selection bits
Divided by 2ⁿ.
© 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 7