MRF24J40 Datasheet, PDF (31/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
7.0 TRANSMITTING AND
RECEIVING PACKETS
7.1 Transmitting Packets
The MAC inside the MRF24J40 will automatically
generate the preamble and Start-of-Frame delimiter
fields when transmitting. Additionally, the MAC can
generate any padding (if needed), and the CRC, if
configured to do so. The host controller must generate
and write all other frame fields into the buffer memory
for transmission. Before transmitting packets, the MAC
registers, which alter the transmission characteristics,
should be initialized as documented in Section 6.0
“Initialization”.
7.2 TX FIFO Format
The TX MAC performs three major tasks conforming to
IEEE 802.15.4:
• TX FIFO Control
• Automatic CSMA-CA and Timing Alignments
• Hardware Superframe Handling
For TX FIFO control function, TX MAC controls
4 FIFOs, including beacon, normal and 2 GTS FIFOs.
When each FIFO is triggered, TX MAC performs a
CSMA-CA algorithm, sends a packet to the Transmit
Baseband (TXBB) at the right time, handles the
retransmission if an ACK is required but not received
and generates FCS bytes automatically.
The automatic CSMA-CA algorithm performs timing
alignments, such as LIFS, SIFS and ACK turnaround
time. The user can simply program parameters for the
CSMA-CA algorithm. The TX MAC will perform
automatically according these parameters.
For hardware superframe handling, TX MAC builds up
the timing frame of a superframe. It includes CAP, CFP,
INACTIVE and each time slot. TX MAC sends beacon,
normal and GTS FIFOs at the right time, automatically, at
each transmission. This largely reduces the complexity of
the Beacon Enable mode of IEEE 802.15.4.
FIGURE 7-1:
TRANSMIT PACKET LAYOUT
Address
Memory
Description
0x000
0x001
0x002-0x003
0x004
0x005
0x005 + (m – 1)
0x006 + m
0x007 + m
Header Length
Packet Length
(m + 3)
Frame Control
Sequence Number
Data[0]
Data[...]
Data[m – 1]
FCS[0]
FCS[1]
Length of the header. This field is described in more
detail in the security section of this document.
The length of the packet, not including the length or FCS.
The frame control field describing how this packet should
behave.
The sequence number distinguishing this packet.
The destination and source addressing information,
as well as any application data.
The CRC value for the packet; written by hardware.
© 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 29