MRF24J40 Datasheet, PDF (23/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
6.0 INITIALIZATION
6.1 Overview
Before the MRF24J40 can be used to transmit and
receive packets, certain device settings must be initial-
ized. Depending on the application, some configuration
options may need to be changed. Normally, these tasks
may be accomplished once after Reset and do not
need to be changed thereafter.
6.2 Receive Filters
To minimize the processing requirements of the host
controller, the MRF24J40 incorporates several different
receive filters which can automatically reject packets
which are not needed. These options are controlled
through the RXMCR register.
REGISTER 6-1: RXMCR: RECEIVE FILTER CONTROL REGISTER
R/W-0
TXCRCEN
bit 7
R/W-0
r
R/W-0
ACKEN
R/W-0
r
R/W-0
PANCOORD
R/W-0
COORD
R/W-0
RXCRCEN
R/W-0
PROMI
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TXCRCEN: No CRC Data with Normal FIFO bit
1 = CRC is disabled for the TX FIFO
0 = CRC is enabled for the TX FIFO
bit 6
Reserved: Maintain as ‘0’
bit 5
ACKEN: No ACK Respond in Any Case bit
1 = ACK response is always disabled
0 = ACK response enabled. ACKs are returned when they are requested.
bit 4
Reserved: Maintain as ‘0’
bit 3
PANCOORD: PAN Coordinator bit
1 = Set as PAN coordinator
0 = Not set as PAN coordinator
bit 2
COORD: Coordinator bit
1 = Set as coordinator
0 = Not set as coordinator
bit 1
RXCRCEN: Error Report bit
1 = RX all kinds of PKT (including CRC error)
0 = Only RX PKT (CRC ok)
bit 0
PROMI: RX All Kinds of PKT bit (CRC ok)
1 = RX all kinds of PKT (CRC ok)
0 = Discard PKT when there is a MAC address mismatch, illegal frame type, dPAN/sPAN or
MAC short address mismatch
© 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 21