MRF24J40 Datasheet, PDF (32/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
7.2.1 TRIGGER PACKET TRANSMISSION
The MRF24J40 handles the Clear Channel Assess-
ment (CCA) and Carrier Sense Multiple Access Colli-
sion Avoidance (CSMA-CA) algorithms in hardware.
The MRF24J40 also handles automatic retransmission
of packets that require an ACK. If the frame control field
of the packet requires an ACK, the ACKREQ bit
(TXNMTRIG<2>) needs to be set before transmission.
Once the TX FIFO is loaded with the data to transmit
the TXRTS bit (TXNMTRIG<0>) is used to transmit the
packet.
REGISTER 7-1: TXNMTRIG: TRIGGER AND SETTING FOR NORMAL FRAME (CAP) REGISTER
U-0
—
bit 7
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
W-0
—
—
PENDACK INDIRECT⁽¹⁾ ACKREQ⁽¹⁾ SECEN⁽¹⁾
TXRTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
PENDACK: Data Pending Status in ACK bit
Status of the data pending bit in ACK from previous transmission. This bit is reset by hardware on the
next transmission.
1 = Data pending bit was set
0 = Data pending bit was cleared
INDIRECT: Activate Indirect Transmission bit⁽¹⁾
1 = Indirect transmission enabled
0 = Indirect transmission disabled
ACKREQ: TX Packet in TXN FIFO needs ACK Response bit⁽¹⁾
1 = ACK requested
0 = No ACK requested
SECEN: Secure Current TX Packet bit⁽¹⁾
1 = Secure packet
0 = Send packet without securing it
TXRTS: Trigger TX MAC to Send the Packet in TX FIFO bit
1 = Send the packet in the TX FIFO, automatically cleared by hardware
Note 1: This bit is cleared at the next triggering of TXN FIFO.
DS39776A-page 30
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© 2006 Microchip Technology Inc.