MRF24J40 Datasheet, PDF (35/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

7.4.1 RECEIVE PACKET LAYOUT
When a packet passes all of the enabled filters, it is
placed in the receive FIFO in the following format.
FIGURE 7-3:
RECEIVE PACKET LAYOUT.
Address
Memory
Description
MRF24J40
0x300
0x301-0x302
0x303
0x304
0x304 + (m – 1)
0x305 + m
0x306 + m
0x307 + m
0x308 + m
Packet Length
(m + 5)
Frame Control
Sequence Number
Data[0]
Data[...]
Data[m – 1]
FCS[0]
FCS[1]
LQI
RSSI
The length of the packet, not including
the packet length, but does include the FCS.
The frame control field describing how this packet should
behave.
The sequence number distinguishing this packet.
The destination and source addressing information
as well as any application data.
The CRC value for the packet; written by hardware.
The link quality index of the received packet.
The received signal strength indicator for the received packet.
© 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 33