MRF24J40 Datasheet, PDF (37/66 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
8.0 INTERRUPTS
The MRF24J40 has a simple interrupt structure. There
is one interrupt pin that signals all of the possible
events. The ISRSTS register is a read-to-clear register
that specifies which interrupt(s) caused the interrupt.
The INTMSK register is used to block unwanted inter-
rupt sources from generating interrupts. The INTEDGE
bit (CLKINTCR<1>) controls the polarity of the interrupt
pin. Once ISRSTS is read by the host controller, the
interrupt flags are cleared. The host controller should
make certain to handle all returned flags each time the
ISRSTS register is read.
FIGURE 8-1:
MRF24J40 INTERRUPT LOGIC
8.1 Interrupt Structure
When an enabled interrupt occurs, the interrupt pin will
remain at its interrupt state, as determined by the
INTEDGE bit, until all of the flags which are causing the
interrupt are cleared or masked off (the mask bits are
set) by the host controller. If more than one interrupt
source is enabled, the host controller must poll each
flag in the ISRSTS register to determine the source(s)
of the interrupt.
ISRSTS.SLPIF
INTMSK.SLPMSK
ISRSTS.WAKEIF
INTMSK.WAKEMSK
ISRSTS.HSYMTMRIF
INTMSK.HSYMTMRMSK
CLKINTCR.INTEDGE
ISRSTS.SECIF
INTMSK.SECMSK
INT
ISRSTS.RXIF
INTMSK.RXMSK
ISRSTS.GTS2TXIF
INTMSK.GTS2TXMSK
ISRSTS.GTS1TXIF
INTMSK.GTS1TXMSK
ISRSTS.TXIF
INTMSK.TXMSK
© 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 35