DSPIC30F5011_06 Datasheet, PDF (85/224 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F5011/5013
13.0 OUTPUT COMPARE MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1, 2, 3,..., N). The dsPIC DSC devices contain up to
8 compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Comparator
OCTSEL
0
1
0
Output
Logic
3
OCM<2:0>
Mode Select
1
From GP
Timer Module
TMR2<15:0
TMR3<15:0> T2P2_MATCH T3P3_MATCH
SQ
R
OCx
Output
Enable
OCFA
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
© 2006 Microchip Technology Inc.
DS70116F-page 83