DSPIC30F5011_06 Datasheet, PDF (49/224 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F5011/5013
6.0 FLASH PROGRAM MEMORY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
The dsPIC30F family of devices contains internal pro-
gram Flash memory for executing user code. There are
two methods by which the user can program this
memory:
1. Run-Time Self-Programming (RTSP)
2. In-Circuit Serial Programming (ICSP)
6.1 In-Circuit Serial Programming
(ICSP)
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manu-
facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
6.2 Run-Time Self-Programming
(RTSP)
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 32 instructions (96 bytes) at a time.
6.3 Table Instruction Operation
Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the effective
address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.
FIGURE 6-1:
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
0
Program Counter
0
Counter
Using
NVMADR
Addressing
1/0 NVMADRU Reg
8 bits
NVMADR Reg EA
16 bits
Using
Table
Instruction
1/0 TBLPAG Reg
8 bits
Working Reg EA
16 bits
User/Configuration
Space Select
24-bit EA
Byte
Select
© 2006 Microchip Technology Inc.
DS70116F-page 47