DSPIC30F5011_06 Datasheet, PDF (65/224 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F5011/5013
8.3 Input Change Notification Module
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor, in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in Sleep mode,
when the clocks are disabled. There are up to 24 exter-
nal signals (CN0 through CN23) that may be selected
(enabled) for generating an interrupt request on a
change of state.
TABLE 8-10: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 15-8)
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset State
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE
00C2
—
—
—
—
—
—
00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
00C6
—
—
—
—
—
—
u = uninitialized bit
CN9IE
—
CN9PUE
—
CN8IE
—
CN8PUE
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLE 8-11: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 7-0)
SFR
Name
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
00C0 CN7IE
00C2
—
00C4 CN7PUE
00C6
—
u = uninitialized bit
CN6IE
—
CN6PUE
—
CN5IE
—
CN5PUE
—
CN4IE
—
CN4PUE
—
CN3IE
—
CN3PUE
—
CN2IE CN1IE
CN18IE CN17IE
CN2PUE CN1PUE
CN18PUE CN17PUE
CN0IE
CN16IE
CN0PUE
CN16PUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLE 8-12: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 15-8)
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset State
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE
00C2
—
—
—
—
—
—
00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
00C6
—
—
—
—
—
—
u = uninitialized bit
CN9IE
—
CN9PUE
—
CN8IE
—
CN8PUE
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLE 8-13: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 7-0)
SFR
Name
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
00C2 CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE
00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE
00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE
u = uninitialized bit
CN0IE
CN16IE
CN0PUE
CN16PUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2006 Microchip Technology Inc.
DS70116F-page 63