DSPIC30F5011_06 Datasheet, PDF (112/224 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F5011/5013
17.4 Message Reception
17.4.1 RECEIVE BUFFERS
The CAN bus module has 3 receive buffers. However,
one of the receive buffers is always committed to mon-
itoring the bus for incoming messages. This buffer is
called the Message Assembly Buffer (MAB). There are
2 receive buffers visible, RXB0 and RXB1, that can
essentially instantaneously receive a complete
message from the protocol engine.
All messages are assembled by the MAB and are trans-
ferred to the RXBn buffers only if the acceptance filter
criterion are met. When a message is received, the
RXnIF flag (CiINTF<0> or CiINRF<1>) will be set. This
bit can only be set by the module when a message is
received. The bit is cleared by the CPU when it has com-
pleted processing the message in the buffer. If the
RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt
will be generated when a message is received.
RXF0 and RXF1 filters with RXM0 mask are associated
with RXB0. The filters RXF2, RXF3, RXF4, and RXF5
and the mask RXM1 are associated with RXB1.
17.4.2 MESSAGE ACCEPTANCE FILTERS
The message acceptance filters and masks are used to
determine if a message in the message assembly
buffer should be loaded into either of the receive buff-
ers. Once a valid message has been received into the
MAB, the identifier fields of the message are compared
to the filter values. If there is a match, that message will
be loaded into the appropriate receive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame,
and only filters with the EXIDE bit set are compared.
Configuring the RXM<1:0> bits to ‘01’ or ‘10’ can
override the EXIDE bit.
17.4.3 MESSAGE ACCEPTANCE FILTER
MASKS
The mask bits essentially determine which bits to apply
the filter to. If any mask bit is set to a zero, then that bit
will automatically be accepted regardless of the filter
bit. There are 2 programmable acceptance filter masks
associated with the receive buffers, one for each buffer.
17.4.4 RECEIVE OVERRUN
An overrun condition occurs when the MAB has
assembled a valid received message, the message is
accepted through the acceptance filters and when the
receive buffer associated with the filter has not been
designated as clear of the previous message.
The overrun error flag, RXnOVR (CiINTF<15> or
CiINTF<14>), and the ERRIF bit (CiINTF<5>) will be
set and the message in the MAB will be discarded.
If the DBEN bit is clear, RXB1 and RXB0 operate inde-
pendently. When this is the case, a message intended
for RXB0 will not be diverted into RXB1 if RXB0 con-
tains an unread message and the RX0OVR bit will be
set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid message is received for RXB0 and
RXFUL = 1 indicates that RXB0 is full and RXFUL = 0
indicates that RXB1 is empty, the message for RXB0
will be loaded into RXB1. An overrun error will not be
generated for RXB0. If a valid message is received for
RXB0 and RXFUL = 1, indicating that both RXB0 and
RXB1 are full, the message will be lost and an overrun
will be indicated for RXB1.
17.4.5 RECEIVE ERRORS
The CAN module will detect the following receive
errors:
• Cyclic Redundancy Check (CRC) Error
• Bit Stuffing Error
• Invalid Message Receive Error
These receive errors do not generate an interrupt.
However, the receive error counter is incremented by
one in case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
17.4.6 RECEIVE INTERRUPTS
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
• Receive Interrupt:
A message has been successfully received and
loaded into one of the receive buffers. This inter-
rupt is activated immediately after receiving the
End-of-Frame (EOF) field. Reading the RXnIF flag
will indicate which receive buffer caused the
interrupt.
• Wake-up Interrupt:
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
DS70116F-page 110
© 2006 Microchip Technology Inc.