PIC24F04KA200 Datasheet, PDF (8/26 Pages) Microchip Technology – Flash Programming Specifications

PIC24FXXKA2XX
3.4 Flash Memory Programming in
ICSP Mode
3.4.1 PROGRAMMING OPERATIONS
The NVMCON register controls the Flash memory write
and erase operations. To program the device, set the
NVMCON register to select the type of erase operation
(see Table 3-2) or write operation (see Table 3-3). Set
the WR control bit (NVMCON<15>) to initiate the
program.
In ICSP mode, all programming operations are
self-timed. There is an internal delay between setting and
automatic clearing of the WR control bit when the
programming operation is complete. Refer to
Section 5.0 “AC/DC Characteristics and Timing
Requirements” for information on the delays associated
with various programming operations.
3.4.2
STARTING AND STOPPING A
PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Initiate the programming cycle by setting
the WR bit.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
is completed. Start a programming cycle as follows:
BSET NVMCON, #WR
TABLE 3-2: NVMCON VALUES FOR
ERASE OPERATIONS
NVMCON
Value
Erase Operation
4064h
Erase the code memory and
Configuration registers (does not erase
programming executive code and
Device ID registers).
404Ch
Erase the general segment and
Configuration bits associated with it.
4068h
405Ah⁽¹⁾
4059h⁽¹⁾
4058h⁽¹⁾
Erase the boot segment and
Configuration bits associated with it.
Erase four rows of code memory.
Erase two rows of code memory.
Erase a row of code memory.
4054h
4058h⁽¹⁾
Erase all the Configuration registers
(except the code-protect fuses).
Erase Configuration registers except
FBS and FGS.
Note 1: The destination address decides the
region (code memory or Configuration
register) of the erased rows/words.
TABLE 3-3: NVMCON VALUES FOR
WRITE OPERATIONS
NVMCON
Value
Write Operation
4004h⁽¹⁾
4004h⁽¹⁾
Note 1:
Write one Configuration register.
Program one row (32 instruction words)
of code memory or executive memory.
The destination address decides the
region (code memory or Configuration
register) of the erased rows/words.
DS39991A-page 8
 2010 Microchip Technology Inc.